Low power current comparator circuit using a cascode transistor structure for bias generation. (March 2022)

• Record Type: Journal Article
• Authors: Casañas, César W.V.; Souza, Gabriel A.F.; Saotome, Osamu; Moreno, Robson L.
• Is Part Of: Microelectronics journal. Volume 121(2022)
• Publication Date: 2022-03
• Subjects: CMOS -- TSMC -- Current mode -- Current comparator -- Flipped voltage follower; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105359
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A novel strategy for the biasing of the input stage in a current comparator circuit is proposed. Instead of using additional current mirrors or other components, such as integrated resistors, a cascode transistor structure is employed in order to bias the flipped voltage follower circuit which is acting as the input stage for the current comparator (CC). The CC was designed, simulated and characterized in CMOS technology with TSMC 0 . 18 μ m process, biased with a current of 5 μ A and nominal process voltage of 1.8 V. A propagation delay of 7.5 ns and an input impedance of 50 Ω were obtained when the input current has an amplitude of ± 350 nA with frequency 50 MHz. The circuit consumes 47 μ W of static power.