Cost-effective schemes for minimizing the delay dispersion of the comparator in level-crossing ADCs applications. (March 2022)

• Record Type: Journal Article
• Authors: Morsi, Mohamed; Atef, Mohamed; Ramzy, Safwat M.
• Is Part Of: Microelectronics journal. Volume 121(2022)
• Publication Date: 2022-03
• Subjects: LC-ADC Comparator -- Signal to noise ratio -- Time-to-digital converter; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105384
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, a cost-effective scheme is presented to reduce the delay dispersion of the comparator in level crossing analog-to-digital converters (LC-ADCs). The proposed scheme involves two different techniques: the first technique, modifying the conventional comparator by adding one p-type transistor as variable driving-current block (VDCB). In the second technique, VDCB which is consisting of two transistors is added to the conventional comparator. The implementation for the two proposed circuits is done by using 130 nm technologies that occupies an active area of 72.8 μ m 2 . The delay dispersion is improved by 18% compared conventional design without VDCB. The results of the second proposed scheme show that the improvement in the delay dispersion is 33%. To substantiate the proposed method, the proposed comparator is also implemented and simulated in 45 nm technology where the delay dispersion is improved by 30% and 40% in the first technique and the second technique, respectively, compared to the conventional comparator.