Capacitance-to-voltage converter employing parallel-series passive charge integrator for low noise power efficient MEMS capacitive sensor. (March 2022)

• Record Type: Journal Article
• Authors: Zhong, Longjie; Shang, Pengpeng; Cao, Wenfei; Zhu, Zhangming; Liu, Shubin
• Is Part Of: Microelectronics journal. Volume 121(2022)
• Publication Date: 2022-03
• Subjects: Terms—Capacitive sensor -- Readout circuit -- Sensor interface -- MEMS accelerometer -- Parasitic capacitance -- Low noise -- Low power -- Power efficient -- Switched-capacitor; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2022.105369
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Parallel-series passive charge integrator (PSPI) based capacitance-to-voltage converter (CVC) is proposed in this paper to reduce the noise floor of readout circuit for MEMS capacitive sensor with high power efficiency in terms of the figure of merit (FoM). For MEMS capacitive accelerometer, open-loop structure is preferred for its low power consumption. However, in the open-loop structure, the capacitance variation of sensing element is limited to femto-farad level in order to overcome nonlinearity. As a result, the thermal noise from parasitic capacitance becomes significant, which leads to low SNR. Traditional oversampling method can reduce the parasitic-induced noise, but leads to low power efficiency. In this work, the PSPI-CVC is proposed to reduce the parasitic-induced noise with high power efficiency. The PSPI-CVC is designed by a commercial 0.18 μm CMOS process. The transistor-level simulation results show that, compared to the traditional CVC, the PSPI-CVC can improve the SNR by 24 dB without increase of the power consumption. Compared with the other similar works, the proposed readout circuit achieves competitive F o M 1 ( F o M 1 = 20.2 p J )and the best F o M 2 ( F o M 2 ).