A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration. (April 2022) - Huang, Yukai; Ding, Jiale; Li, Dengquan; Zhao, Xin; Liu, Shubin; Shen, Yi; Zhu, Zhangming
Abstract: This paper presents a nonbinary 2b/cycle SAR ADC structure with two assistant loop-unrolled comparators. By using the reset time of 2-bit comparators, the proposed structure achieves extra single bit conversion after normal 2-bit conversions, thus removing one comparison period compared with conventional 2-bit SAR. A nonbinary decision scheme is realized to relax the DAC voltage settling requirement, especially the signal-DAC voltage for loop-unrolled conversion. Besides, a low kick back noise comparator is adopted with time-based offset calibration, which reduces DAC voltage fluctuation and eliminate offset mismatch. Simulation result shows that the ADC achieves 53.35 dB SNDR at Nyquist input frequency after offset calibration, resulting in a Walden FoM of 28.76fJ/conversion-step.