A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS. (April 2022) - Mao, Henghui; Li, Dengquan; Liu, Shubin
Abstract: This paper proposes a high-speed 7/8-bit 800-400 MS/s configurable SAR ADC. With simple control switches, the ADC can work under two different modes with configurable resolution and sampling speed. Nonbinary technique with built-in redundancy in capacitive DAC is used for better linearity as well as improving the conversion speed. Other high-speed techniques, such as spilt switching scheme, asynchronous clock, are also utilized to further increase the conversion speed. A design example in 65 nm CMOS is presented. Simulation results show that with 1.2 V supply, the SNDR at Nyquist input are 43.40 dB and 49.57 dB under 7-bit (800 MS/s) mode and 8-bit (400 MS/s) mode, respectively. The power consumptions are 2.17 mW and 1.36 mW for 7-bit and 8-bit modes, respectively. Therefore, the calculated Walden FOM for 7-bit mode is 22.3 fJ/conversion step and 14.2 fJ/conversion step for 8-bit mode.