A 0.6-V 12-bit 13.2-fJ/conversion-step SAR ADC with time-domain VCDL-based comparator and metastability immunity technique. (April 2022) - Tong, Xingyuan; Jin, Wei; Zhang, Chunming; Xin, Xin; Dong, Siwan; Li, Qinqin
Abstract: A 0.6-V 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) is presented in this paper. Compared with the conventional time-domain comparator, the latch-like phase detector can reduce the dead zone voltage because of the positive feedback structure. Furthermore, a low power metastability immunity technique is proposed to suppress the uncertain decision-making behavior at the small input differences. The simulation results show that the proposed SAR ADC can achieve a 73.75-dB signal-to-noise and distortion ratio (SNDR) and consume 3.6 μW power consumption at the Nyquist input and sampling rate of 100 kS/s, resulting in a figure-of-merit (FOM) of 13.2 fJ/Conversion-step. Meanwhile, the core area is only 0.197 mm 2 with the fully customized MOM capacitor array in a 0.18-μm CMOS process.