Progressive p-channel vertical transistors fabricated using electrodeposited copper oxide designed with grain boundary tunability. Issue 3 (5th January 2022)

• Record Type: Journal Article
• Authors: Jung, Sung Hyeon; Yang, Ji Sook; Kim, Young Been; Deshpande, Nishad G.; Kim, Dong Su; Choi, Ji Hoon; Suh, Hee Won; Lee, Hak Hyeon; Cho, Hyung Koun
• Is Part Of: Materials horizons. Volume 9:Issue 3(2022)
• Page Start: 1010
• Page End: 1022
• Publication Date: 2022-01-05
• Subjects: Materials -- Research -- Periodicals; 543.0284
• DOI: 10.1039/d1mh01568k
• Languages: English
• ISSNs: 2051-6347

Abstract

Abstract : In this study, we designed a new transistor structure without spacers using an electrodeposition method for the active layer. We strategically utilized grain boundary tunability for the fabrication of spacer-free p-type vertical transistors. Abstract : A strategically designed electrodeposition method is proposed for the coating of p-type copper(i) oxide (Cu2 O) channels for oxide thin film transistors. To date, conventional p-type oxide semiconductors have revealed a poor mobility and stability and this has obstructed the development of all oxide based logic devices. Furthermore, previous studies on p-type oxide transistors have been limited by the use of a typical planar type configuration. Our Cu2 O electrodeposition method designed by incorporating Sb element promotes vertical alignment of the grain boundaries (GBs) and it perfectly coincides with the charge transport direction from the source to the drain in the vertical field effect transistors. These vertically aligned GBs are bundle type GBs and are likely to be ideal for vertical transistors with supreme electrical performances owing to the structurally suppressed grain boundary charge scattering. This alignment of the GBs in the electrodeposited Sb doped Cu2 O (Sb:Cu2 O) also demonstrates a superior vertical taper profile with conventional wet chemical etching owing to the extremely preferential etching rate along the GBs. Surprisingly, the sidewall formation, with a smooth and steep morphology causes the formation of abrupt and non-defective gate insulator/channel interfaces for superior spacer-free vertical transistors. Consequently, the Cu2 O vertical field effect transistors exhibit extraordinary transistor performances of V th = 0.4 V, μ FE = 8 cm 2 V −1 s −1, subthreshold swing = 0.24 V dec −1, on/off current ratio = 2 × 10 8 and qualified electrical and long-term stability characteristics under various environments. To the best of our knowledge, this is the first reported study on an electrodeposited method to design troublesome p-type oxide Cu2 O as novel vertical transistors. Finally, power efficient logic inverter circuits with unprecedented performances, such as good noise margins, remarkable gain values of 15.6 (2 V DD ) and 62.7 (5 V DD ), and high frequency operation up to 10 kHz, are demonstrated using these p-type Cu2 O transistors by interconnecting n-type IGZO transistors.