Flash Lamp Annealed LTPS TFTs with ITO Bottom-Gate Structures. (8th September 2020)

• Record Type: Journal Article
• Authors: Packard, Glenn; Rosenfeld, Adam; Manley, Robert G.; Hirschman, Karl D.
• Is Part Of: ECS transactions. Volume 98:Number 7(2020)
• Page Start: 141
• Page End: 150
• Publication Date: 2020-09-08
• Subjects: Electrochemistry -- Periodicals; Electrochemistry; Periodicals; Electronic journals; Electronic journal; 541.37
• DOI: 10.1149/09807.0141ecst
• Languages: English
• ISSNs: 1938-5862

Abstract

Abstract : A study on bottom-gate PMOS TFTs built on flash lamp annealed polycrystalline silicon is presented. As an alternative to top-gate devices, bottom-gate TFTs offer potential benefits in dielectric-semiconductor interface quality due to process integration details of crystallization and defect passivation. Indium Tin Oxide was used as the gate electrode material due to its attractive optical and electrical properties, thermal stability, and compatibility with the FLA process. Details of an experimental design used to investigate combinations of FLA and furnace annealing for a-Si crystallization and dopant activation processes will be discussed. ITO Bottom-gate TFTs fabricated with FLA crystallization followed by boron ion implantation and furnace activation exhibited superior electrical characteristics in comparison to other treatments. A comparison of electrical characteristics measured on bottom-gate and double-gate devices is used to develop an interpretation of defect effects and provide a qualitative assessment of interface states.