Performance evaluation of gate engineered InAs–Si heterojunction surrounding gate TFET. (February 2022) - Sathishkumar, M.; Samuel, T.S. Arun; Ramkumar, K.; Anand, I. Vivek; Rahi, S.B.
Abstract: In semiconductor industry, at nanoscale dimensions, numerous field effect devices have been proposed and investigated for further improvement in performance of low power circuit and system. In the present research report, a novel low power FET device structure namely: Surrounding Gate Triple Material Heterojunction Tunnel Field Effect Transistor (SGTM-heTFET) has been proposed with the analytical modeling approach. The benefits of surrounding gate and tunnel FETs are coupled to create a new structure, to decrease short channel effects. Three different gate materials with different work functions replace the gate material that surrounds the device. An analytical model of surface potential(ψ), electric field(E) and drain current (IDS ) have been developed for SGTM-heTFET. With the use of low work function material such as 4.0eV, 4.6eV and 4.0eV, the proposed model shows a better ON current of 10 −5 A/μm for a VGS of 0.7V, ON-OFF ratio of 10 10 with the sub-threshold swing of 50mV/dec. The developed model's for SGTM-heTFET shows excellent device characteristics and have been verified using TCAD simulation, ensuring the model's accuracy. Highlights: A Novel device structure called Surrounding Gate Triple Material Heterojunction TFET is proposed. The electrical parameters are analytically calculated and also compared with the simulated output. Along with triple material, hetero-dielectric (HfO2 /SiO2 ) arrangement is also proposed to reduce leakage current. Improved ON current and ION /IOFF ratio is achieved with SS less than 60mV/dec.