A precise clock distribution network for MRPC-based experiments. (14th June 2016)

• Record Type: Journal Article
• Authors: Wang, S.; Cao, P.; Shang, L.; An, Q.
• Is Part Of: Journal of instrumentation. Volume 11:Number 6(2016:Jun.)
• Page Start: C06006
• Page End: C06006
• Publication Date: 2016-06-14
• Subjects: Hardware and accelerator control systems -- Instrumentation for particle accelerators and storage rings - high energy (linear accelerators, synchrotrons); Scientific apparatus and instruments -- Periodicals; 502.84
• DOI: 10.1088/1748-0221/11/06/C06006
• Languages: English
• ISSNs: 1748-0221

Abstract

Abstract: In high energy physics experiments, the MRPC (Multi-Gap Resistive Plate Chamber) detectors are widely used recently which can provide higher-resolution measurement for particle identification. However, the application of MRPC detectors leads to a series of challenges in electronics design with large number of front-end electronic channels, especially for distributing clock precisely. To deal with these challenges, this paper presents a universal scheme of clock transmission network for MRPC-based experiments with advantages of both precise clock distribution and global command synchronization. For precise clock distributing, the clock network is designed into a tree architecture with two stages: the first one has a point-to-multipoint long range bidirectional distribution with optical channels and the second one has a fan-out structure with copper link inside readout crates. To guarantee the precision of clock frequency or phase, the r-PTP (reduced Precision Time Protocol) and the DDMTD (digital Dual Mixer Time Difference) methods are used for frequency synthesis, phase measurement and adjustment, which is implemented by FPGA (Field Programmable Gate Array) in real-time. In addition, to synchronize global command execution, based upon this clock distribution network, synchronous signals are coded with clock for transmission. With technique of encoding/decoding and clock data recovery, signals such as global triggers or system control commands, can be distributed to all front-end channels synchronously, which greatly simplifies the system design. The experimental results show that both the clock jitter (RMS) and the clock skew can be less than 100 ps.