Analysis of nanoscale digital circuits using novel drain-gate underlap DMG hetero-dielectric TFET. (January 2022) - Gracia, D.; Nirmal, D.; Moni, D. Jackuline
Abstract: In this paper, the investigation of dual metal double gate (DMG) hetero-dielectric TFET with drain-gate underlap for nanoscale digital applications is analyzed. Drain-gate underlap TFET is used to achieve lower ambipolar current (Iambi ) and low leakage current (Ioff ) than a conventional hetero-dielectric TFET. The performance analysis has been done in terms of bias dependent parasitic capacitances. Results reveal that drain-gate underlap suppresses the gate-drain capacitance by 5.6% than the conventional DMG TFET which in turn has a positive effect on the digital applications. The prime performance metrics such as rising/falling delay, propagation delay and peak overshoot voltages are analyzed for drain-gate underlap DMDG TFET inverter. The propagation delay and the overshoot voltage show significant decrease of 9.27% and 1.24% respectively for the drain-gate underlapped TFET for a supply voltage (Vdd ) of 0.5V. Thus the drain-gate underlap TFET is considered to be a good candidate for nanoscale digital applications. Highlights: The incorporation of drain-gate underlap for nanoscale digital applications is investigated for Ge based DMG TFET inverter. Drain-gate underlap DMG TFET has reduced Cgd and hence the overall performance metrics of the inverter is improved. Drain-gate underlap suppresses the gate-drain capacitance by 5.6% than the conventional DMG TFET. The propagation delay and the overshoot voltage show significant decrease of 9.27% and 1.24% respectively for for a Vdd of 0.5V. Thus the drain-gate underlap TFET is considered to be a good candidate for nanoscale digital applications.