An integrated 0.0625–4 GHz quadrature-output fractional-N frequency synthesizer for software-defined radios. (January 2022)

• Record Type: Journal Article
• Authors: Yao, Yan; Li, Zhiqun; Li, Zhennan; Chen, Bofan; Wang, Xiaowei
• Is Part Of: Microelectronics journal. Volume 119(2021)
• Publication Date: 2022-01
• Subjects: Frequency synthesizer -- PLL -- SDR -- CMOS -- Fractional-N -- Phase noise; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105334
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a compact 0.0625–4 GHz fractional-N frequency synthesizer with quadrature phase output for software-defined radios (SDRs). Four voltage controlled oscillators (VCOs) and six cascaded dividers are used for wideband operation. Second harmonic filtering and high frequency noise suppression techniques are applied in VCO for phase noise optimization. Inverter switch and cascade switch buffers are combined for channel selection enhancement and output amplitude improvement. A large output voltage dynamic range with minimum current variation and mismatch is achieved by enabling transistors to work in triode region in charge pump. Implemented in a 55 nm CMOS process, the synthesizer demonstrates continuous frequency coverage from 62.5 to 4000 MHz with orthogonal output signals greater than 2 dBm while consuming 125 mW of power and provides the phase noise performance of −96.3/-127.7 dBc/Hz at 10 kHz/1 MHz offsets under a 2 GHz carrier. The chip area including all the pads and IOs is 3.34 mm 2 .