Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier. (January 2022)

• Record Type: Journal Article
• Authors: Saha, Aloke; Singh, Rakesh Kumar; Pal, Dipankar
• Is Part Of: Microelectronics journal. Volume 119(2021)
• Publication Date: 2022-01
• Subjects: Delay equalization -- Double pass-transistor logic (DPL) -- Pair-wise multiplication strategy -- Ternary multiplier -- Vedic Urdhava Tiryagbhyam (UT) sutra -- Wave pipelining; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105318
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Multiplier acts as a central building block for most digital computations, hence is of major significance and concern in improving speed-power-reliability in digital processing systems. High-resolution-need for modern, sophisticated computing system has put binary (base-2) multipliers under question mark due to large interconnect-overhead, reliability-issue and market-relevance. Digital multiplication by ternary (base-3) numbers can effectively reduce aforesaid drawbacks associated with binary based multiplication. Present study introduces a novel ternary multiplier based on Vedic Urdhava-Tiryagbhyam (UT) Sutra with Pair-Wise strategy and wave-pipelining. The Double Pass-transistor Logic (DPL) has been applied to complete the front-end circuit design in order to achieve high-speed ternary multiplication with low-power dissipation through efficient wave-pipelining. The complete circuit has been designed on 32 nm CMOS technology on 1.0 V supply rail at 27 °C temperature. The trit input "0", "1" and "2" are coded with 0 V, 0.5 V and 1.0 V respectively. The design is validated through extensive T-Spice simulation with all possible test patterns at 27 °C temperature. Next the physical design of proposed multiplier has been done and the post layout simulation with all parasitic are performed. Comparative study with recent candidate designs is presented. Finally, the effect of PVT (Process-Voltage-Temperature) variation on proposed multiplier has been investigated and recorded.