Timing Selector: Using Transient Switching Dynamics to Solve the Sneak Path Issue of Crossbar Arrays. Issue 1 (10th October 2021)

• Record Type: Journal Article
• Authors: Rao, Mingyi; Song, Wenhao; Kiani, Fatemeh; Asapu, Shiva; Zhuo, Ye; Midya, Rivu; Upadhyay, Navnidhi; Wu, Qing; Barnell, Mark; Lin, Peng; Li, Can; Wang, Zhongrui; Xia, Qiangfei; Joshua Yang, J.
• Is Part Of: Small science. Volume 2:Issue 1(2022)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2021-10-10
• Subjects: crossbar arrays -- memristors -- neuromorphic computing -- resistive switching -- selectors; Nanoscience -- Periodicals; Nanotechnology -- Periodicals; 620.5
• DOI: 10.1002/smsc.202100072
• Languages: English
• ISSNs: 2688-4046

Abstract

Abstract : Sneak path current is a fundamental issue and a major roadblock to the wide application of memristor crossbar arrays. Traditional selectors such as transistors compromise the 2D scalability and 3D stack‐ability of the array, while emerging selectors with highly nonlinear current–voltage relations contradict the requirement of a linear current–voltage relation for efficient multiplication by directly using Ohm's law. Herein, the concept of a timing selector is proposed and demonstrated, which addresses the sneak path issue with a voltage‐dependent delay time of its transient switching behavior, while preserving a linear current–voltage relationship for computation. Crossbar arrays with silver‐based diffusive memristors as the timing selectors are built and the operation principle and operational windows are experimentally demonstrated. The timing selector enables large memristor crossbar arrays that can be used to solve large‐dimension real‐world problems in machine intelligence and neuromorphic computing. Abstract : A timing selector is proposed, which can utilize its nonlinear relation between switching time and voltage (instead of current and voltage in traditional selectors) to block sneaking current in memristive crossbar arrays. The operation principles are formulated together with experimental demos using integrated one‐selector‐one‐memristor (1S1M) structures.