Design and analysis of a high-performance 90-101 GHz CMOS power amplifier. Issue 1 (2nd January 2022) - Lin, Yo-Sheng; Lan, Kai-Siang
ABSTRACT: A three-stage four–way 90–101 GHz power amplifier (PA) on 90 nm CMOS is reported. The PA consists of a meandrous four-way Wilkinson power divider, and common-source (CS) input and gain stages with inductive shunt-shunt feedback, followed by four-way CS output stage using a compact four-way current combiner. Wideband π-match inter-stage networks are used for broadband impedance and power matching. An LC input network (constituting a series capacitor, a parallel inductor, and an inductive shunt-shunt feedback) is used to convert the input impedance of the input-stage transistors to 50 Ω. This is the way to attain impedance matching at the outputs of the four-way Wilkinson power divider. Besides, an LC output network (constituting a series LC and a parallel inductor) is used to convert the 50 Ω load to the needed series RL load of the four-way current combiner. As a whole, the output-stage transistors operated at the maximal output power (Pout ) and power-added efficiency (PAE). At 94 GHz, the PA attains gain of 20.1 dB, saturated Pout (Psat ) of 17.5 dBm, and maximal PAE (PAEmax ) of 17.7%, one of the best results ever reported for W-band CMOS PAs. The remarkable performance of the CMOS PA reveals its potential for 94 GHz radar systems.