A phase-locked loop with an improved dynamic response under abnormal grid conditions. (January 2022)

• Record Type: Journal Article
• Authors: Smadi, Issam A.; Sultan, Wafa'a
• Is Part Of: Computers & electrical engineering. Volume 97(2022)
• Publication Date: 2022-01
• Subjects: DC offset -- Harmonics -- Delayed signal cancelation -- Phase detection -- Grid synchronization -- Coefficient diagram method; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2021.107645
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: An improved PLL is proposed for grid synchronization under abnormal conditions. The PLL is not restricted to a specific time delay in canceling the dc offset. An accurate small-signal model is provided for the proposed PLL. The coefficient diagram method is adopted for the loop filter design. The PLL requires less than two grid cycles to synchronize with the grid. Abstract: The cascaded delayed signal cancelation (CDSC) method has attracted much attention recently as an efficient filtering technique to improve synchronous reference frame phase-locked loop (PLL) performance in grid synchronization under adverse grid conditions. The CDSC-based PLL suffers from slow transient response. Therefore, this study proposes a solution for grid synchronization under abnormal conditions utilizing an arbitrary time-delay operator to mitigate the DC offset and frequency adaptive CDSC operators for harmonic filtering. An accurate small-signal model was derived, opening the door to design the loop filter. The coefficient diagram method was adopted to systematically design the gains of the proportional–integral controller and a lead–lag compensator, yielding a faster dynamic response than the symmetrical optimum method-based design. The proposed PLL effectiveness was verified numerically under abnormal conditions, showing better dynamic and steady-state performance than other related PLLs. The proposed PLL requires less than two grid cycles to synchronize without ripples, meeting the grid code's requirement. Graphical abstract: Image, graphical abstract