Developed configuration of stacked multicell topology with reduced DC voltage sources. (7th June 2021)
- Record Type:
- Journal Article
- Title:
- Developed configuration of stacked multicell topology with reduced DC voltage sources. (7th June 2021)
- Main Title:
- Developed configuration of stacked multicell topology with reduced DC voltage sources
- Authors:
- Hazrati, Sara
Bannae Sharifian, Mohammad Bagher
Feyzi, Mohammad Reza
Babaei, Ebrahim - Abstract:
- Summary: Multilevel inverters are considered as a suitable alternative for the two‐level topology in the medium‐voltage, high‐power applications because of the higher number of voltage levels, and, as a result, reduced harmonic distortion. One of the most critical types of multilevel inverters is the flying capacitor topology, in which the stacked multicell topology is derived from this type of multilevel inverters. This paper presents a developed configuration of the stacked multicell topology, constructed from 2 m × n primary commutation cells, which generates the output voltage of (2 m × n )+1 levels. The most crucial point in the flying capacitor‐based topologies is balancing the flying capacitors' voltages, which is the primary condition of these topologies' correct operation. Also, in this topology, the number of required DC voltage sources is decreased compared to the existing multicell topology. Moreover, the developed topology can generate a higher number of voltage levels without cascading several cells. The developed multicell inverter topology is controlled based on the disposition band carrier and phase‐shifted carrier sinusoidal pulse width modulation (DBC‐PSC‐SPWM) method. Because of this control method, the voltages of capacitors are self‐adjusted at their value. The proposed topology is simulated in different conditions using PSCAD/EMTDC software and to show the validity of the proposed topology and the control method, and simulation results areSummary: Multilevel inverters are considered as a suitable alternative for the two‐level topology in the medium‐voltage, high‐power applications because of the higher number of voltage levels, and, as a result, reduced harmonic distortion. One of the most critical types of multilevel inverters is the flying capacitor topology, in which the stacked multicell topology is derived from this type of multilevel inverters. This paper presents a developed configuration of the stacked multicell topology, constructed from 2 m × n primary commutation cells, which generates the output voltage of (2 m × n )+1 levels. The most crucial point in the flying capacitor‐based topologies is balancing the flying capacitors' voltages, which is the primary condition of these topologies' correct operation. Also, in this topology, the number of required DC voltage sources is decreased compared to the existing multicell topology. Moreover, the developed topology can generate a higher number of voltage levels without cascading several cells. The developed multicell inverter topology is controlled based on the disposition band carrier and phase‐shifted carrier sinusoidal pulse width modulation (DBC‐PSC‐SPWM) method. Because of this control method, the voltages of capacitors are self‐adjusted at their value. The proposed topology is simulated in different conditions using PSCAD/EMTDC software and to show the validity of the proposed topology and the control method, and simulation results are demonstrated. A laboratory‐type experimental setup is used to validate the modulation strategy and other findings. Abstract : This paper presents a developed configuration of the stacked multicell topology, constructed from 2 m × n primary commutation cells, which generates the output voltage of (2 m × n )+1 levels. In the proposed topology, the number of required DC voltage sources is decreased. The developed multicell inverter topology is controlled based on the disposition band carrier and phase‐shifted carrier sinusoidal pulse width modulation method. Because of this control method, the voltages of capacitors are self‐adjusted at their value. … (more)
- Is Part Of:
- International journal of circuit theory and applications. Volume 49:Number 12(2021)
- Journal:
- International journal of circuit theory and applications
- Issue:
- Volume 49:Number 12(2021)
- Issue Display:
- Volume 49, Issue 12 (2021)
- Year:
- 2021
- Volume:
- 49
- Issue:
- 12
- Issue Sort Value:
- 2021-0049-0012-0000
- Page Start:
- 3941
- Page End:
- 3965
- Publication Date:
- 2021-06-07
- Subjects:
- disposition band carrier pulse width modulation -- multilevel inverter -- phase‐shifted carrier sinusoidal pulse width modulation -- self‐voltage balancing -- stacked multicell
Electric circuit analysis -- Periodicals
621.319205 - Journal URLs:
- http://onlinelibrary.wiley.com/ ↗
- DOI:
- 10.1002/cta.3040 ↗
- Languages:
- English
- ISSNs:
- 0098-9886
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 4542.167000
British Library DSC - BLDSS-3PM
British Library STI - ELD Digital store - Ingest File:
- 20237.xml