Hot-carrier evaluation of a zero-cost transistor developed via process optimization in an embedded non-volatile memory CMOS technology. (November 2021) - Devoge, P.; Aziza, H.; Lorenzini, P.; Julien, F.; Marzaki, A.; Malherbe, A.; Mantelli, M.; Cabout, T.; Delalleau, J.; Haendler, S.; Regnier, A.; Niel, S.
Abstract: A new transistor architecture is developed by reusing already existing fabrication process bricks in an embedded non-volatile memory (eNVM) sub-40 nm CMOS technology, resulting in a middle-voltage zero-cost transistor, ideal for low-cost products. TCAD simulations are undertaken to confirm the feasibility of the process optimization and predict the transistor performance and reliability. The new transistor is fabricated then electrically characterized. The new device shows good analogue performances for no cost added. A hot-carrier injection (HCI) degradation evaluation is performed and confirms the reliability of the device. Highlights: Zero-cost. In low-cost and high-volume products, low-cost transistor architectures are highly desirable.