LC-TSL: A low-cost triple-node-upset self-recovery latch design based on heterogeneous elements for 22 nm CMOS. (November 2021)

• Record Type: Journal Article
• Authors: Huang, Zhengfeng; Pan, Shangjie; Wang, Hao; Liang, Huaguo; Ni, Tianming
• Is Part Of: Microelectronics journal. Volume 117(2021)
• Publication Date: 2021-11
• Subjects: Soft error -- Reliability -- Triple-node-upset -- Single event upset (SEU) -- Self-recovery; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105281
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: With the continuous scaling of CMOS feature sizes, single event triple-node-upset (TNU) induced by charge sharing has become a serious reliability issue. This paper presents a low-cost triple-node-upset self-recovery latch (LC-TSL) which is composed of N-elements, P-elements and C-elements. The LC-TSL utilizes a two-dimensional feedback array composed of four rows and four columns to achieve triple-node-upset recovery. It utilizes high-speed transmission path to achieve high performance and clock-gating to reduce power consumption. The extensive simulation results show that the LC-TSL achieves high speed, low power consumption and 100% TNU recovery. Compared with the average of previous eight hardened latches, the LC-TSL reduces the delay by 78.59% and reduces the power-delay-product by 79.69%, while only increases 15.15% area overhead and 15.38% power consumption overhead. Compared with TNU self-recoverable latches, the LC-TSL is the best in terms of area, delay, and PDP. The LC-TSL achieves TNU-recovery ability and low cost overhead, and it is insensitive to voltage and temperature variations.