Systematic Control of Negative Transconductance in Organic Heterojunction Transistor for High‐Performance, Low‐Power Flexible Ternary Logic Circuits. Issue 46 (11th October 2021)

• Record Type: Journal Article
• Authors: Lee, Chungryeol; Choi, Junhwan; Park, Hongkeun; Lee, Changhyeon; Kim, Chang‐Hyun; Yoo, Hocheon; Im, Sung Gap
• Is Part Of: Small. Volume 17:Issue 46(2021)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2021-10-11
• Subjects: asymmetric source/drain -- heterojunction transistors -- multi‐valued logic circuits -- negative transconductance -- threshold‐voltage shift; Nanotechnology -- Periodicals; Nanoparticles -- Periodicals; Microtechnology -- Periodicals; 620.5
• DOI: 10.1002/smll.202103365
• Languages: English
• ISSNs: 1613-6810

Abstract

Abstract: Organic multi‐valued logic (MVL) circuits can substantially improve the data processing efficiency in highly advanced wearable electronics. Organic ternary logic circuits can be implemented by utilizing the negative transconductance (NTC) of heterojunction transistors (H‐TRs). To achieve high‐performance organic ternary logic circuits, the range of NTC in H‐TRs must be optimized in advance to ensure the well‐defined intermediate logic state in ternary logic inverters (T‐inverters). Herein, a simple and efficient strategy, which enables the systematic control of the range and position of NTC in H‐TRs is presented. Each thickness of p‐/n‐type semiconductor in H‐TRs is adjusted to control the channel conductivity. Furthermore, asymmetric source/drain ( S/D ) electrode structure is newly developed for H‐TRs, which can adjust the amount of hole and electron injection, independently. Based on the semiconductor thickness variation and asymmetric S/D electrodes, the T‐inverter exhibits full‐swing operation with three distinguishable logic states, resulting in unprecedentedly high static noise margin (≈48% of the ideal value). Moreover, a flexible T‐inverter with an ultrathin polymer dielectric is demonstrated, whose operating voltage is less than 8 V. The proposed strategy is fully compatible with the conventional integrated circuit design, which is highly desirable for broad applicability and scalability for various types of T‐inverter production. Abstract : An intermediate logic state of ternary logic circuit is optimized by semiconductor thickness engineering and asymmetric source/drain structure. Both strategies enable independent control of channel conductivity in heterojunction transistors, allowing the negative transconductance to be modulated systematically. The flexible ternary logic inverter is demonstrated for the first time, which exhibits three distinguishable logic states with an unprecedentedly high noise margin.