A new ASIC implementation of an advanced encryption standard (AES) crypto-hardware accelerator. (November 2021)

• Record Type: Journal Article
• Authors: Ahmad, Nabihah; Hasan, S.M.Rezaul
• Is Part Of: Microelectronics journal. Volume 117(2021)
• Publication Date: 2021-11
• Subjects: AES -- Encryption -- Decryption -- Composite-field -- Low-power -- High throughput -- Low chip-area -- Hardware accelerator; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105255
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Single-chip hardware implementation of Advanced Encryption Standard (AES) offers a low-power and low-area design that is suitable for portable devices. It is widely applicable for numerous encryption needs such as in Bluetooth controller, wireless communication and secure Internet transactions. This paper proposes a new full-custom compact 8-bit data-path architecture core for a single-chip VLSI AES crypto-hardware accelerator. In order to optimize chip-area, power and performance, novel circuit-level techniques, logic minimization, resource sharing and low supply-voltage has been employed. The proposed design is implemented in 130 nm CMOS process and supports both encryption and decryption in Electronic-Codebook-Mode (EBC) using 128-bit keys. Novel S-box/InvS-box, MixColumn/InvMixColumn and ShiftRow/InvShiftRow using low-power Exclusive-OR (XOR) gate is employed to minimize the power consumption. This design utilized 3120 gate-equivalents (GE), including an on-the-fly key scheduling unit with an active chip-area of 640μm × 325 μm (0.208 sq. mm) excluding the bonding pads. It has a power consumption of 4.23 μW/MHz and a throughput of 0.05 Gbit/s (at 100 MHz clock). The proposed AES design thus achieved low-power dissipation, higher throughput with a compact chip-size (silicon-area) compared to other recent implementations.