A novel PVT‐variation‐tolerant Schmitt‐trigger‐based 12T SRAM cell with improved write ability and high ION/IOFF ratio in sub‐threshold region. (5th September 2021)

• Record Type: Journal Article
• Authors: Gupta, Monica; Gupta, Kirti; Pandey, Neeta
• Is Part Of: International journal of circuit theory and applications. Volume 49:Number 11(2021)
• Page Start: 3789
• Page End: 3810
• Publication Date: 2021-09-05
• Subjects: hold failure probability -- HSNM -- ION/IOFF ratio -- process variations -- read failure probability -- RSNM -- Schmitt‐trigger -- sub‐threshold -- Vmin -- WM -- write failure probability; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.3134
• Languages: English
• ISSNs: 0098-9886

Abstract

Abstract: This paper presents a process voltage temperature (PVT)‐variation‐tolerant Schmitt‐trigger‐based 12T SRAM cell at 32 nm. The cell uses a modified Schmitt‐trigger action in all operating modes for performance improvement, a characteristic that is not exhibited by existing SRAM cells. The action improves the stability of stored data in read and hold modes and assists the write process to enable a faster and low‐voltage write operation. Additionally, the cell uses negative bitline technique and fully‐gated grounded scheme for achieving further improvement in write ability and ION /IOFF ratio. The proposed cell shows 34.9% reduced deviation in switching threshold voltage in comparison to conventional structure. Further, improvement of up to 211% in write ability and 169% in ION /IOFF ratio is obtained over existing SRAM cells operating in sub‐threshold region. The cell takes up to 86% and 99% lesser read and write access time, respectively. The Monte‐Carlo simulations show the robust performance of proposed cell. The cell has reduced write, read, and hold failure probabilities resulting in overall Vmin of 425 mV, which is the least among the cells considered for comparison, thus making it an amenable design suitable for sub‐threshold operation under PVT‐variations. Abstract : This work proposes a Schmitt‐trigger‐based 12T SRAM cell to overcome the drawbacks associated with conventional structure and trade‐off existing in latest SRAM cell designs at lower technology nodes. It uses modified Schmitt‐trigger action in all operating modes along with negative bitline technique and fully gated grounded scheme for performance improvement under PVT‐variations and reduction in minimum supply voltage.