A 5 MHz-BW 71.7-dB SNDR two-step hybrid-domain ADC in 65-nm CMOS. (November 2021)

• Record Type: Journal Article
• Authors: Yu, Zhe; Liang, Yuhua; Liu, Shubin
• Is Part Of: Microelectronics journal. Volume 117(2021)
• Publication Date: 2021-11
• Subjects: Hybrid-domain -- Analog-to-digital converter (ADC) -- Two-step ADC -- Successive approximation register (SAR) -- Voltage-to-time converter (VTC) -- Noise-shaping -- Time-to-digital converter (TDC); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105253
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper proposes a second-order sigma-delta two-step hybrid-domain ADC comprises of a SAR ADC, a voltage-to-time converter (VTC), and a second-order sigma-delta TDC with all the arithmetic circuits based on the time-registers implemented in time-domain, and the TDC achieves pole-optimization using a method similar to the voltage-domain noise shaping ADC. The SAR ADC samples the input signal and performs the coarse quantization in voltage-domain. Then the residual voltage is transferred into the time signal by the VTC and the TDC completes the fine quantization in time-domain. The prototype ADC is implemented in TSMC 65 nm 1P9M 1.2 V standard CMOS process. The simulated SFDR and SNDR are 75.7 and 71.7 dB with an oversampling ratio of 10 while consuming 4.8 mW at 100 MS/s.