A scalable high‐speed hybrid 1‐bit full adder design using XOR‐XNOR module. (22nd July 2021) - Hasan, Mehedi; Islam, Sharnali; Hossain, Mainul; Zaman, Hasan U.
Abstract: High‐speed XOR‐XNOR‐based hybrid full adder (FA) using a combination of three logic techniques (transmission gate [TG], conventional CMOS [CCMOS], pass transistor [PT]) is presented in this work. Performance analysis and validation of the FA design presented in this work have been realized with reference to 10 state‐of‐the‐art FAs. The scalability of the design has been tested by extending FA up to 32‐bits in ripple carry adder (RCA) style. It has been observed that only four existing FAs and the proposed FA could be scaled up to 32‐bits without including voltage restoration buffers in the internal stages. The proposed XOR‐XNOR‐based FA showed excellent performance metrics, both as a 1‐bit adder cell as well as in wide word length adder form. Hence, the proposed XOR‐XNOR‐based hybrid FA can serve as a better alternative to the existing FAs in digital arithmetic blocks of modern microprocessors. Abstract : A high‐speed, hybrid, and scalable full adder based on XOR‐XNOR module is proposed. Using 45‐nm technology node in Cadence, the design has been analyzed as 1‐bit cell and 32‐bit extended structure in ripple carry adder style. The proposed full adder demonstrated excellent performance as 1‐bit cell and 32‐bit extended structure compared to the existing full adder designs.