A low-power twiddle factor addressing architecture for split-radix FFT processor. (November 2021)

• Record Type: Journal Article
• Authors: Liu, Mingjin; Zhao, Ping; Wu, Tianshu; Parhi, Keshab K.; Zeng, Xiaoyang; Chen, Yun
• Is Part Of: Microelectronics journal. Volume 117(2021)
• Publication Date: 2021-11
• Subjects: Split-radix fast fourier transform (SRFFT) -- Twiddle factor -- Single-delay feedback -- Low-power -- Pipelining; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105276
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The split-radix fast Fourier transform (SRFFT) is attractive for low-power FFT processors as it has the lowest numbers of multiplication operations among all FFT algorithms. FFT algorithms differ from one another by the location of the twiddle factor. The irregular locations of the twiddle factors in the SRFFT lead to complex address generators for the memory containing the twiddle factors. This paper proposes a novel twiddle factor addressing architecture for the split-radix FFT processor, which can effectively reduce its power consumption. This is then used to design a simple memory address generator and a low-power pipelined SRFFT. The proposed algorithm is used to implement a 1024-point pipelined circuit. Post-layout simulation shows that the proposed 1024-point design achieves over 24% and 14.7% lower power consumption for the multiplications and ROM, respectively, compared to a traditional radix-2 single delay feedback (SDF) FFT architecture. Highlights: In this paper, a novel twiddle factor addressing architecture is proposed, which can reduce the power consumption of the SRFFT processor. Under the TSMC 65 nm process, we compared the newly proposed SRFFT processor with the traditional radix-2 FFT processor. SRFFT processor can reduce the power consumption of the multiplier by 24% and the power consumption of the ROM by 14.7%.