Low-latency area-efficient systolic bit-parallel GF(2m) multiplier for a narrow class of trinomials. (November 2021) - Pillutla, Siva Ramakrishna; Boppana, Lakshmi
Abstract: Edge computing in Internet of Things (IoT) requires high-performance as well as cost-effective hardware implementations to accommodate large number of computations. Implementation of security in IoT edge devices is indispensable, and attaining security is possible using Elliptic curve cryptography (ECC) algorithms. Finite field GF (2 m ) multiplication is a performance-critical operation in these algorithms, hence, it requires efficient hardware implementations. Systolic structures for GF (2 m ) multiplier are suitable for high-performance applications as they allow high-throughput implementations. Many systolic GF (2 m ) multipliers have been proposed in the literature that can achieve high throughput rates, however, they require large area and high latency. In this paper, we propose a polynomial basis GF (2 m ) systolic multiplier applicable for a narrow class of trinomials which includes both the NIST (National Institute of Standards and Technology) recommended trinomials for m = 233 and 409 fields. Analytical comparisons with the related multipliers for m = 409 show that the multiplier proposed in this paper reduces the latency by 32% and area by 5%. The proposed multiplier is synthesized using synopsis tools targeting for an ASIC implementation and the comparisons are also presented. The proposed low-latency area-efficient multiplier can be used in the implementation of hardware security for low-cost IoT edge devices.