Addressing source to drain tunneling in extremely scaled Si-transistors using negative capacitance. (December 2021) - Pandey, Nilesh; Pahwa, Girish; Chauhan, Yogesh Singh
Highlights: An analytical model of MFIS-NCFET, including the impact of source/drain depletion regions over the device electrostatic, is developed. The developed model accurately captures the 2-D electrostatic (conduction band energy) and quantum transport of the device. Using the NCFET the scaling limit which is primarily imposed by DSDT can be pushed to ∼ 7 nm gate length with SS < 80 mV/dec and IOFF < 60 nA/ μ M compared to 173 mV/dec and 1.5 × 10 6 nA/ μ M, respectively for the baseline at the same gate length. Under the severe subthreshold tunneling circumstances, we find that although NC mitigates the thermionic Boltzmann tyranny, it is ineffective in suppressing the subthreshold swing beyond a limit. A critical value of ferroelectric thickness ( t e 0 ) is calculated. It has shown that increasing the ferroelectric thickness above t e 0 will not improve the subthreshold slope (see Fig. 7). Therefore, the NC if ineffective in the severe tunneling region. Abstract: The impact of negative capacitance (NC) of the ferroelectric materials in controlling the direct source to drain tunneling (DSDT) in ultra-short channel FETs is presented in this paper. Besides, an analytical model is developed by solving 2-D Poisson's equation incorporating the degeneracy of source/drain (S/D) regions. We demonstrate that in NC gate stack based Si channel FETs (NC-FETs), the scaling limit can be pushed down to 7 nm gate length, without using effective mass engineering and alternate channel materials. However, under severe subthreshold tunneling circumstances, we find that as the % content of tunneling current rises above the value of 50% in the net current, the subthreshold slope (SS) ceases to improve with the higher ferroelectric thickness. The rigorous analysis of DSDT-Negative drain induced barrier lowering (NDIBL) and impact of the S/D doping over DSDT is also incorporated in the paper. It is found that DSDT decreases drastically in the NCFET compared to baseline FETs due to the NC effect. Hence, using NC effect, transistor can be scaled down to 7 nm physical gate length with SS < 80 mV/dec and I OFF < 70 nA / μ m compared to 173 mV/dec and 1.5 × 10 6 nA / μ m, respectively for the baseline FET at the same gate length.