An adaptive core mapping algorithm on NoC for future heterogeneous system-on-chip. (October 2021)

• Record Type: Journal Article
• Authors: Kumar, Aruru Sai; Rao, T.V.K. Hanumantha
• Is Part Of: Computers & electrical engineering. Volume 95(2021)
• Publication Date: 2021-10
• Subjects: System-on-Chip (SoC) -- Network-on-Chip (NoC) -- Core -- Fault tolerance -- Spare core placement; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2021.107441
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: An adaptive core mapping algorithm, which dynamically recovers the failed cores in an application, helps improve system performance. Core Mapping simulations carried out through the Noxim simulator for various routings algorithms (such as XY, WEST-FIRST, NORTH-LAST, and ODD-EVEN). Hardware Verification is synthesized and simulated using Vivado Design Suite 2018.3 and verified on the Kintex-7 FPGA KC705 board. The results showed a significant improvement in terms of energy consumption, delay, and throughput. Abstract: The mapping analysis needs to have a complete performance assessment of Network-on-Chip (NoC) based on delay, throughput, and energy consumption measurements. This paper proposes an Adaptive Core Mapping (ACM) algorithm, which can dynamically react and recover from the failed core through spare core replacement to maintain system functionality. The core mapping methodology considered the complete performance evaluation for different routing algorithms. Mapping simulations executed on the NoC Simulator (Noxim), adjusted to perform a re-enactment for various routing algorithms, such as XY, WEST-FIRST, NORTH-LAST, and ODD-EVEN routings. A significant improvement observed in energy consumption, average delay, and throughput in the proposed work compared with existing algorithms. The proposed adaptive core mapping algorithm is synthesized and simulated using Vivado Design Suite 2018.3 and verified on the Kintex-7 FPGA KC705 board. The performance parameters, such as area, power consumption, and throughput, are obtained. The results show that the proposed algorithm is helpful for less area, power consumption, and high-speed applications in the NoC environment.