Power-Aware Alternative Adder Cell Structure Using Swing Restored Complementary Pass Transistor Logic at 45nm Technology. (2015)

• Record Type: Journal Article
• Authors: Bhagyalaxmi, T.; Rajendar, S.; Srinivas, S.
• Is Part Of: Procedia materials science. Volume 10(2015)Supplement
• Page Start: 789
• Page End: 792
• Publication Date: 2015
• Subjects: swing restored complementary pass transistor logic -- adder cell -- logic style -- low power -- power-delay-product; Materials science -- Congresses; Materials science -- Periodicals; Materials science; Conference proceedings; Periodicals; 620.11
• DOI: 10.1016/j.mspro.2015.06.021
• Languages: English
• ISSNs: 2211-8128

Abstract

Abstract: In this paper, a novel low power 20T alternative adder cell featuring modified swing restored complementary pass transistor logic (SR-CPL) is proposed. This alternative adder cell structure performs better in terms of power dissipation, propagation delay and power-delay-product (PDP) when compared with 26T SR-CPL and other adder cells implemented using conventional logic styles. As compared with 26T SRCPL adder cell, the proposed adder cell reduces power by 23.15%, delay by 6.15% and PDP by 27.91%. This design is carried-out using a TSMC 45 nm CMOS technology in Cadence Virtuoso Analog Design Environment at 45 nm technology and simulated using Spectre simulator. This adder cell can be used as a computation element in various DSP architectures and microprocessors resulting in high performance.