Harvard architecture based post processed True random number generator. (2021)

• Record Type: Journal Article
• Authors: Saranya, M.; Revathy, M.; Kaleel Rahuman, A.
• Is Part Of: Materials today. Volume 47:Part 1(2021)
• Page Start: 135
• Page End: 138
• Publication Date: 2021
• Subjects: True Random Number Generators -- FPGA -- Jitter -- Ring oscillator -- Programmable Delay Lines; Materials science -- Congresses -- Periodicals; 620.1
• DOI: 10.1016/j.matpr.2021.04.019
• Languages: English
• ISSNs: 2214-7853

Abstract

Abstract: The True random number generation (TRNG) is a process which takes different physical quantities that should be non-deterministic in nature and then they are post processed to reduce potential biases in the random number generation process. The true random number generators are used in various applications like security, cryptography, computer simulation and gaming applications. This work proposed a unique and powerful approach to get random numbers on FPGA by using an unsystematic jitter of ring oscillators. In order to get wide range of variations in the oscillations and to inject jitter into the generated ring oscillator clocks, the free running oscillator rings integrate programmable delay lines (PDL). The primary advantage of the proposed true random number generator is that it regulates the resemblance between many ring oscillators and so it improves the randomness qualities by using PDL. Furthermore, a Harvard architecture based post processing unit is used to eradicate similarities in the generated random numbers. Validation of the suggested solution synthesized on Xilinx with the support of Verilog HDL, and the parameters in terms of area, delay and power are also analyzed.