Analysis of admittance measurements of MOS capacitors on CVD grown bilayer MoS2. (22nd May 2019)

• Record Type: Journal Article
• Authors: Gaur, Abhinav; Chiappe, Daniele; Lin, Dennis; Cott, Daire; Asselberghs, Inge; Heyns, Marc; Radu, Iuliana
• Is Part Of: 2D materials. Volume 6:Number 3(2019)
• Publication Date: 2019-05-22
• Subjects: 2D materials -- MX2 -- admittance -- capacitance -- interface traps -- MoS2 -- 2D MOS capacitor; Graphene -- Periodicals; Materials science -- Periodicals; Nanostructured materials -- Periodicals; 620.115
• DOI: 10.1088/2053-1583/ab20fb
• Languages: English
• ISSNs: 2053-1583

Abstract

Abstract: In this study we present results on the AC admittance response of bilayer MoS2 films grown using chemical vapor deposition. A new MOS capacitor design for ultra-thin body 2D materials is proposed. We show that along with the density of interface traps ( D it ), a transverse electric field distribution in the semiconductor and parasitic capacitance also cause frequency dispersion in measured capacitance. D it extracted using the conductance method in 40 devices indicates reliable measurements for channel length, L < 10 m. For devices with L > 10 m, an increase in D it is an artifact of access resistance in the semiconductor. Temperature measurements show an increasing defect distribution from cm −2 eV −1 around mid-gap to cm −2 eV −1 close to the conduction band minimum.