Reduced-Complexity LDPC Decoding for Next-Generation IoT Networks. (22nd September 2021)

• Record Type: Journal Article
• Authors: Asif, Muhammad; Khan, Wali Ullah; Afzal, H. M. Rehan; Nebhen, Jamel; Ullah, Inam; Rehman, Ateeq Ur; Kaabar, Mohammed K. A.
• Other Names: Morosi Simone Academic Editor.
• Is Part Of: Wireless communications and mobile computing. Volume 2021(2021)
• Publication Date: 2021-09-22
• Subjects: Wireless communication systems -- Periodicals; Mobile communication systems -- Periodicals; 621.38205
• DOI: 10.1155/2021/2029560
• Languages: English
• ISSNs: 1530-8669

Abstract

Abstract : Low-density parity-check (LDPC) codes have become the focal choice for next-generation Internet of things (IoT) networks. This correspondence proposes an efficient decoding algorithm, dual min-sum (DMS), to estimate the first two minima from a set of variable nodes for check-node update (CNU) operation of min-sum (MS) LDPC decoder. The proposed architecture entirely eliminates the large-sized multiplexing system of sorting-based architecture which results in a prominent decrement in hardware complexity and critical delay. Specifically, the DMS architecture eliminates a large number of comparators and multiplexors while keeping the critical delay equal to the most delay-efficient tree-based architecture. Based on experimental results, if the number of inputs is equal to 64, the proposed architecture saves 69%, 68%, and 52% area over the sorting-based, the tree-based, and the low-complexity tree-based architectures, respectively. Furthermore, the simulation results show that the proposed approach provides an excellent error-correction performance in terms of bit error rate (BER) and block error rate (BLER) over an additive white Gaussian noise (AWGN) channel.