FPGA Implementation Framework for Explicit Hybrid Model Predictive Control. (2020)

• Record Type: Journal Article
• Authors: Patne, Vaishali; Ingole, Deepak; Sonawane, Dayaram
• Is Part Of: IFAC-PapersOnLine. Volume 53(2020)Supplement
• Page Start: 362
• Page End: 367
• Publication Date: 2020
• Subjects: Mixed logical dynamical systems -- model predictive control -- optimization -- FPGA -- inverted pendulum -- Hybrid MPC; Automatic control -- Periodicals; 629.805
• DOI: 10.1016/j.ifacol.2020.06.061
• Languages: English
• ISSNs: 2405-8963

Abstract

Abstract: Hybrid systems can be controlled by a Hybrid Model Predictive Control (HMPC) with an accurate prediction model and proper formulation. In the real-time evolution of HMPC, an online optimization (mostly, Mixed Integer Quadratic Programming (MIQP)) problem needs to be solved at each sample time. Online implementation of MIQP solver on resource-limited embedded platforms poses challenges, which limits its use for the slow dynamic systems. The online burden of MIQP solver can be moved offline by multi-parametric programming. In this paper, we present an implementation of explicit HMPC on Field Programmable Gate Array (FPGA) for the control of Mixed Logical Dynamical (MLD) systems. We show the step-by-step procedure of FPGA implementation of HMPC considering the model of the inverted pendulum. In the implementation, we used MATLAB-based Hybrid Toolbox to construct hybrid MPC and subsequently generate a low-level C/C++ code of the HMPC. Further, the generated C/C++ code is optimized for memory, speed, and resource utilization by the customized approach of applying pipelining and directives using Xilinx Vivado. The customized explicit HMPC is then implemented on a Xilinx ZYNQ-7000 SoC ZC706 FPGA. The implemented approach is compared with the linear (online and explicit) MPC with a linearized model of the system. The detailed analysis of controller computational complexity in terms of memory, resource utilization, clock, and power consumption is presented. The performance of implemented HMPC is verified through Hardware-in-the-Loop (HIL) co-simulations.