A 1.8‐V 240‐MHz 2.19‐mW Four‐Stage CMOS OTA with a Segmenting Frequency Compensation Technique. Issue 5 (1st September 2021)

• Record Type: Journal Article
• Authors: Yuhua, LIANG; Zirui, ZHENG; Shubin, LIU; Dengquan, LI; Ruixue, DING; Zhangming, ZHU
• Is Part Of: Chinese journal of electronics. Volume 30:Issue 5(2021)
• Page Start: 853
• Page End: 860
• Publication Date: 2021-09-01
• Subjects: Four‐stage amplifiers -- Frequency compensation -- Segmenting nested Miller compensation; Electronics -- Periodicals; Electronics -- China -- Periodicals; Electronics; China; Periodicals; 621.38105
• DOI: 10.1049/cje.2021.06.007
• Languages: English
• ISSNs: 1022-4653

Abstract

Abstract : A four‐stage Operational transconductance amplifier (OTA) used in an infrared temperature sensor adopting the proposed Feed‐forward Gm ‐stage and segmenting nested Miller compensation technique is presented. The purpose of the proposed segment compensation is primarily to make more amplifier stages concatenated. The circuit linked several transconductance stages to form a segment, and linked several segments to form a large multistage amplifier. For example, a two‐stage amplifier linked with a three‐stage amplifier can realize a five‐stage amplifier, two three‐stage amplifiers linked can realize a six‐stage amplifier. A four‐stage amplifier in the form of 2+2 (two stages and two stages) was used as an example to verify this compensation method. The proposed OTA is designed in the 180nm complementary metal oxide semiconductor process. It consists of two parts which ensure the stability and improve the bandwidth performance. The first part is a feed‐forward transconductance stage, and the second part is the two‐segment transconductance stages with the Miller compensation techniques employed within and between the two segments. Based on the small‐signal model, stability analysis and theoretical derivation are performed in theory. On condition of a 2‐pF load capacitance, a direct current gain of 109dB and a gain‐bandwidth of 240MHz with a phase margin of 50° can be achieved. The proposed design consumes 2.19mW in a 1.8‐V supply voltage. The transient simulation indicates that the settling time of the output is 19ns with the settling error being 1%, and the slew rate is 114V/μs.