Cite
HARVARD Citation
Sreenivasulu, V. et al. (2021). Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. Microelectronics journal. p. . [Online].
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Sreenivasulu, V. et al. (2021). Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. Microelectronics journal. p. . [Online].