Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. (October 2021) - Sreenivasulu, V. Bharath; Narendar, Vadthiya
Abstract: In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire field-effect-transistor (FET) for significantly enhanced performance at sub-5 nm nodes. The symmetric and asymmetric spacer lengths are optimized and compared towards the improvement of subthreshold swing (SS) and switching ( I O N I O F F ) behavior with various spacer dielectrics. For optimal values of source ( L S ) and drain ( L D ) spacer lengths, the device I O N I O F F ratio has an improvement of 22.69% and a reduction in I O F F by 34.13% as compared to other variations. Our study reveals that, in symmetric spacer variations the device exhibits superior performance with L S = L D = 1 . 5 × L G . However, compared to symmetric, the asymmetric spacer exhibits higher I O N I O F F and lower SS with L S = 1 . 5 × L G and L D = 2 . 5 × L G . Moreover, L G scaling impact on SS, DIBL, V t h, and I O N are reported with various spacers. The optimized asymmetric spacer exhibits excellent DC characteristics with SS of 64 mV/dec and I O N I O F F ratio of ∼ 10 8 even for 5 nm gate length ( L G ) ensures fundamental scaling. At L G of 10 nm with asymmetric spacer, a cut-off frequency ( f T ) = 0.4 THz, gain-bandwidth product (GBW) = 0.08 THz, and intrinsic delay ( τ ) = 1.3 ps are achieved. Finally, the device exhibits second order harmonic ( g m 2 ) = 0.2 mA/ V 2 and third order harmonic ( g m 3 ) = 1.1 mA/ V 3 at nano-regime. Thus optimally designed JL nanowire FET ensures potential candidate towards low-power, high frequency, and better linearity for future technology nodes.