A 1.2 GHz jitter-peaking-free Integer-N PLL. (October 2021)

• Record Type: Journal Article
• Authors: Yaghobi, Hossein; Tavakoli, Javad; Sheikhaei, Samad
• Is Part Of: Microelectronics journal. Volume 116(2021)
• Publication Date: 2021-10
• Subjects: Voltage controlled oscillator -- Jitter-peaking -- Phase-locked-loop (PLL) -- Voltage controlled delay line (VCDL) -- Phase noise; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105246
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In conventional charge-pump PLLs, if the third high-frequency pole is ignored, the system comprises of two poles and a zero. The transfer function of such a system is second-order low pass, which in some part of its frequency spectrum, the amplitude response | H | goes above unity. This translates to jitter-peaking, which in turn amplifies the input phase noise. Depending on damping factor or ζ, this jitter-peaking could be large or small. In this paper, a dual-path PLL with an additional Voltage Controlled Delay Line (VCDL) is presented that removes the jitter-peaking by adjusting the frequency values of the zero and poles in the PLL transfer function. In this new architecture, by increasing the VCO's gain ( K vco ) the output phase noise is reduced. Designed and simulated in 65 nm CMOS and operating with a reference frequency of 12.5 MHz, the proposed PLL provides a spur level of −45dBc. The presented PLL exhibits an in-band phase noise of − 117 dBc / Hz at 1 MHz offset and total power consumption of 10.5 mW. Graphical abstract: Image 1