Vertical traversal approach towards TSVs optimisation over multilayer network on chip (NoC). (October 2021) - Panem, Charanarur; Gad, Rajendra S.; Kaushik, Brajesh Kumar
Abstract: In symmetric 3-D chip stacking, TSVs plays an important role and provides denser and fine pitches. The number of vertical links in 3-D mesh NoC topology is equal to 2 ( N − ( N 2 3 ) ), where N is the number of network nodes. The TSVs use pads for establishing a connection between the layers, which could generate the misalignment issue due to chip warpage, thermal stress, and TSVs cross-coupling, which notifies a maximum permitted density of TSVs Keep-Out Zone. The study has discussed the analytical model of the seven-port router to express an average number of packets at equilibrium conditions for the physical and virtual channel and demonstrated the performance model. The latency objective function is deduced over reduced global interconnect and algorithm proposed for adaptive XYZ routing, in support of TSV placement scheme. Later the analytical model is emulated for practical significance. Highlights: Study has discussed the analytical model of seven port routers to express the average number of packets at equilibrium conditions over the physical and virtual channel. Proposed configuration of sphere-based vertical traversal leading to TSV's density optimization for average numbers of packets at equilibrium over multilayer NoC, with a suitable algorithm for XYZ routing. Evaluated the robustness of such sphere-based vertical traversal configuration for fault-tolerant using random breaking links over NoC mesh topology in various percentages from 0% to 20% over multilayer 18x18 3D NoC. Analyzed the performance metrics over such virtual channel configuration for throughput and latency over CBR & FTP applications. The said study proposed optimization of TSV's to identify the keep-out zone parameter.