PFD with improved average gain and minimal blind zone combined with lock-in detection for fast settling PLLs. (October 2021)

• Record Type: Journal Article
• Authors: H.K., Ravi; Mukherjee, Jayanta
• Is Part Of: Microelectronics journal. Volume 116(2021)
• Publication Date: 2021-10
• Subjects: Phase frequency detector -- Average gain -- Blind zone -- Lock-in detection -- Settling time -- Phase-locked loop; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105233
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, two Phase frequency detector (PFD) architectures and a PFD with lock-in detection (PFD-LID) are proposed that are designed using the new techniques for selectively resetting the outputs to achieve improved average gain with a lower blind zone. The two proposed PFDs are designed and fabricated using 180 nm CMOS process. The circuits are tested with the variations in the supply voltage from 1.3 V to 1.8 V, achieving higher average gain and the measured blind zone of 3 ps, which is around five times less than earlier reported works. Also, the proposed selective reset techniques are used to design the PFD-LID. Both the PFDs and PFD-LID are validated using the traditional phase-locked loop (PLL) architecture by achieving minimal settling time of the PLL.