A transient enhanced cap-less low-dropout regulator for wide range of load currents and capacitances. (September 2021)

• Record Type: Journal Article
• Authors: P., Manikandan; B., Bindu
• Is Part Of: Microelectronics journal. Volume 115(2021)
• Publication Date: 2021-09
• Subjects: Low dropout regulator -- Flipped voltage follower -- Super source follower -- Settling time -- System-on-chip; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105207
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: In this paper, a transient enhanced flipped voltage follower (FVF) based cap-less low-dropout (LDO) regulator for wide range of load currents and capacitances is presented. The proposed LDO uses a slow–fast loop architecture with three feed-forward paths to enhance the transient behaviour and to stabilize the feedback loop. These feed-forward paths help to eliminate the minimum load current and load capacitance constraints with improved transient responses. A simple damping-ratio enhancer (DRE) is used to stabilize the loop further. This LDO provides the regulated power supply voltage of 1 V with good load and line regulations. It achieves the settling time of 200 ns with the minimum edge time of 100 ps for the load currents from 0 to 50 mA and the load capacitance ranges from 0 to 2 nF. The proposed LDO is implemented in 130 nm CMOS technology and consumes only a quiescent current of 95 μ A.