A high-speed and scalable XOR-XNOR-based hybrid full adder design. (July 2021) - Hasan, Mehedi; Hussain, Md. Shahbaz; Hossain, Mainul; Hasan, Mohd.; Zaman, Hasan U.; Islam, Sharnali
Highlights: Many full adders having high-performance are not scalable to multiple bits Hybrid full adders tend to have better performance than single logic cells Mirror full adder is better than many recent designs in multiple bit operation Abstract: This work presents the design of a scalable and full-swing Full Adder (FA) based on the XOR-XNOR module. The performance of the design has been compared with eleven existing state-of-the-art FAs. The proposed FA obtains 19.35% improvement in Silicon area, 33.59% improvement in Average Power, 36.15% improvement in Propagation Delay, 56.22% improvement in Area Delay Product (ADP), and 57.59% improvement in Power Delay Product compared to the conventional Mirror CMOS FA. Moreover, performance parameters have been examined in wide adder structures by extending the FAs to 32-bits without adding level restoring buffers in the intermediate stages. The obtained simulation data suggest that the proposed FA and 5 out of the 11 existing FAs can be practically scaled up to 32-bits. The proposed FA showed superior performance in the 32-bit operation. Because of the improved features, the proposed hybrid FA can be a reliable and superior alternative to existing FAs. Graphical Abstract: Image, graphical abstract