Constant delay systolic binary counter with variable size cellular automaton based prescaler. (July 2021)

• Record Type: Journal Article
• Authors: Chioktour, Vasileios; Kakarountas, Athanasios
• Is Part Of: Computers & electrical engineering. Volume 93(2021)
• Publication Date: 2021-07
• Subjects: Counter -- Digital circuit -- Cellular automata -- Systolic structure -- High throughput; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2021.107291
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: An One-Dimension (1D) Cellular Automaton (CA) is studied as a generator for the radix-2 sequence, presenting suitable characteristics for the design of a fast and constant delay synchronous digital counter. The main contribution of this work is the proposal of a new type of synchronous digital counters including a CA-based prescaler and consecutive counting modules of various configurations (in terms of bitlength, speed and area requirements) to result in a modular and systolic counting structure with the minimum redundant hardware and low-power operation. It is the first time that a thorough exploration of the 1D CA rule 102 is offered and considered as the prescaler of a systolic counter of heterogeneous modules in size, achieving the desired constant delay characteristic with low area/power penalty. The proposed counter, compared to hard Intellectual Property (IP) cores, presents up to 90% enhancement of speed for 9.37%–33.0% area penalty for reconfigurable technologies.