An energy-efficient crypto-extension design for RISC-V. (September 2021)

• Record Type: Journal Article
• Authors: Wang, Weizhen; Han, Jun; Cheng, Xu; Zeng, Xiaoyang
• Is Part Of: Microelectronics journal. Volume 115(2021)
• Publication Date: 2021-09
• Subjects: RSIC-V -- Internet-of-Things -- Cryptography extension -- Energy-efficient design -- Conditional-charged flip-flop -- Application Specific Instruction-Set Processor (ASIP); Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105165
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: With the prevailing of Internet-of-Things (IoT) technology, information security for ever-growing connected devices is an inevitable issue and gaining more attention. However, implementation of cryptography algorithms on battery-powered IoT devices is challenging due to limited power-budget. In this paper, we present an energy-efficient crypto-coprocessor. This coprocessor is designed with a unified pipelined structure for cryptography primitives of 128-bit or 256-bit data path and supports cryptography algorithms including AES, ECC and SHA. Since the clock tree and the sequential circuits dissipate a large percentage of the chip power, a conditional-charged flip-flop is proposed to reduce the clock tree power. Our design is integrated with an open-sourced RISC-V core as a crypto-extension, and shows both good flexibility and high energy-efficiency. This work is implemented in 28 nm technology and the power consumption for different cryptography applications is evaluated with post-layout simulation. When simulated with NIST prime fields curve P-256 and binary fields curve K-233, the energy consumed for one base point scalar multiplication is 43.54 μ J and 20.40 μ J, respectively. The proposed design consumes 0.0568 nJ/bit and 0.0288 nJ/bit for the AES-GCM mode and the AES-CBC mode, respectively. As for SHA-256, each bit requires 0.0874 nJ. Compared with previous works, this work provides both flexibility and high energy performance. Highlights: A coprocessor with unified 4-stage pipelined structure for cryptography is proposed. The coprocessor is integrated with RISC-V and evaluated in 28 nm technology. A flip-flop is proposed and achieves 47.5% power reduction for the coprocessor.