Precise realization of one-staged 2-D DCT using analog current mode architecture in compressed sensing front-end. (September 2021)

• Record Type: Journal Article
• Authors: Ganguly, Anirban; Banerjee, Ayan
• Is Part Of: Microelectronics journal. Volume 115(2021)
• Publication Date: 2021-09
• Subjects: DCT -- CS -- TPS -- ABCM -- Cascoding; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105184
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Analog discrete cosine transform (DCT) with CMOS image sensor is an advantageous alternative in low power wireless Compressed Sensing (CS) Systems. The researchers have made some attempts in the recent past behind analog 2D-DCT using switched-capacitor (SC) and current mirror that follow conventional cascaded DCT technique. But these techniques lack accuracy due to capacitor mismatch and circuit-level noises on the DCT symbol. This approach presents a novel algorithm (using product-to-sum method and periodicity of cosine function) to obtain a computational block for current-mode circuit realization of 2D-DCT in a single stage. Cascoded current mirror in the circuit ensures higher accuracy in computation. Rigorous simulation of proposed circuit in SPICE with 65 nm CMOS process showed the supremacy of the architecture. The power consumption can be kept minimal to 12.1 mW for 8*8 2-D DCT during the computation of 64 output symbols using conventional class-AB current mirror. With dynamic biasing strategy, this can be reduced to even less than 3 mW. The circuit simulated DCT symbols were tested in a CS block model at different compression ratios (CR).