Performance Optimization of Analog Circuits in Negative Capacitance Transistor Technology. (September 2021)

• Record Type: Journal Article
• Authors: Prakash, Om; Chauhan, Nitanshu; Gupta, Aniket; Amrouch, Hussam
• Is Part Of: Microelectronics journal. Volume 115(2021)
• Publication Date: 2021-09
• Subjects: Current mirror -- Negative Differential Resistance -- Negative Capacitance -- NC-FET -- Analog circuits -- Ferroelectric -- Emerging technology -- Steep-slope transistor; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105193
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Negative Capacitance Field-Effect Transistor (NC-FET) is one of the emerging technology for the future ultra-low power circuits. NC-FET incorporates a ferroelectric layer within the transistor gate stack, which provides an internal voltage amplification. However, Negative Differential Resistance (NDR), which occurs at thick ferroelectric can deteriorate NC-FET devices in which the drain current, in the saturation region, decreases with drain voltage increase. This noticeably harms the figure of merits of circuits, especially when it comes to analog applications. This work presents a detailed analysis on the correlation between ferroelectric thickness and NDR effects using well-calibrated TCAD infrastructure for 14 nm FDSOI. For the first time, a novel extension length modulation technique is proposed to mitigate NDR effects effectively. Our technique allows designers to optimize the combination of ferroelectric thickness and extension length in which NDR effects are well suppressed, thereby maximizing the performance and gain of analog circuits.