A low complexity bit parallel polynomial basis systolic multiplier for general irreducible polynomials and trinomials. (September 2021)

• Record Type: Journal Article
• Authors: Devi, Sakshi; Mahajan, Rita; Bagai, Deepak
• Is Part Of: Microelectronics journal. Volume 115(2021)
• Publication Date: 2021-09
• Subjects: Finite fields -- Polynomial basis -- Bit parallel -- Systolic multiplier; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105163
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The bit parallel multiplication scheme is characterized by an important feature called concurrency, which makes its execution faster. The output through this scheme is generated in every clock cycle, after taking 'm' clock cycles in the beginning. In this paper, a polynomial basis systolic multiplier over irreducible polynomials ( x m + t m − 1 x m − 1 + . . .. t 2 x 2 + t 1 x 1 + t 0 ) in GF(2 m ) is designed specifically for odd 'm', which takes 'm' clock cycles and this is further, used to design the low complexity bit-parallel architecture for general irreducible polynomials and trinomials ( x m + x k + 1 ). The area complexity of the proposed multiplier for general irreducible polynomials matches with the best existing multiplier with a 17% reduction in time complexity due to a considerable decrease in critical path delay. To the best of our knowledge, the area-delay product of the proposed multipliers is the lowest achieved when compared with the best multipliers available in the literature. FPGA implementation results also show that the proposed multiplier has 59% less space complexity and 47% less time complexity than the best-reported multiplier for m = 233.