Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET. (15th March 2021)

• Record Type: Journal Article
• Authors: Ashita, ; Loan, Sajad A.; Alkhammash, Hend I.; Rafat, Mohammad
• Other Names: Vadalà Valeria guestEditor.; Crupi Giovanni guestEditor.
• Is Part Of: International journal of numerical modelling. Volume 34:Number 5(2021)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2021-03-15
• Subjects: lateral pocket -- perpendicular gate‐pocket configuration -- gate over source -- pre‐aligned paths; Electric networks -- Mathematical models -- Periodicals; Electronics -- Mathematical models -- Periodicals; 621.3011
• DOI: 10.1002/jnm.2877
• Languages: English
• ISSNs: 0894-3370

Abstract

Abstract: In this work, we propose and investigate a new pocket‐based Si0.55 Ge0.45 /Si gate normal tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with and without a heterogeneous dielectric (HD) gate oxide. Miller capacitance is significantly reduced with the GSLP design, which is further improved by the HD gate oxide leading to full overshoot/undershoot suppression capability in transient response. Further, a steep switching with more than one order improvement in ON current is achieved when compared to state‐of‐the‐art line pocket designs. As a result, an ~98.8% and ~88% improved intrinsic delay ( C GG V DD / I ON ) is achieved in comparison to dual line pocket and non‐pocketed designs, respectively. Additionally, an improved worst‐case trap‐charge tolerance, reduced pocket‐width‐induced fluctuations, and excellent immunity to gate misalignment‐induced fluctuations are achievable just by replacing the gate‐aligned parallel‐line pockets with a vertically aligned single‐lateral pocket (LP) improving the design reliability. A Ge/Si HD‐GSLP TFET design further offers stable ON currents with SS < 60 mV/dec over a feasible range of pocket widths between ~6 and 8 nm at V DS = V GS = 0.7 V.