Design of unbalanced ternary counters using shifting literals based D-Flip-Flops in carbon nanotube technology. (July 2021)

• Record Type: Journal Article
• Authors: Sharma, Trapti; Kumre, Laxmi
• Is Part Of: Computers & electrical engineering. Volume 93(2021)
• Publication Date: 2021-07
• Subjects: Carbon nanotube field effect transistor -- Multiple valued logic design -- Ternary logic -- Counter design; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2021.107249
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Digital computation using multi-valued logic decreases the requirement of interconnections which leads to a reduction in the power consumption, energy consumption and chip area in digital system design. Among various sequential logic elements, a counter is the main block that is repeatedly used for counting purposes in several processor applications. This work presents the methodology to design asynchronous and synchronous counter designs using three valued logic. The circuit implementation includes shifting operators for the D-flip-flop and counter realization in carbon nanotube technology. To realize optimized shifting circuits efficient voltage divider topology is employed by exploiting the most appropriate on-state current capability of active P-type and N-type transistors. The unique characteristic of carbon nanotube field-effect transistors (CNTFETs) to control the threshold voltage of the device by adjusting the CNT diameter favors their suitability for ternary design implementation. Thereafter, for the performance assessment of the proposed designs, simulations are conducted using the 32 nm CNTFET model using the Synopsys HSPICE simulator. Simulation results confirm the reduction in power consumption and Power delay product(PDP) of 51% and 69% for 3-bit asynchronous counter and 46% and 47% respectively for 2-bit synchronous counter design. Also, the proposed counter design shows the satisfactory operation and works reliably when simulated under different test conditions of temperature, voltage, and process variations.