Design and simulation of an innovative CMOS ternary 3 to 1 multiplexer and the design of ternary half adder using ternary 3 to 1 multiplexer. (August 2019)

• Record Type: Journal Article
• Authors: Jahangir, Mohd Ziauddin; Mounika, J.
• Is Part Of: Microelectronics journal. Volume 90(2019)
• Page Start: 82
• Page End: 87
• Publication Date: 2019-08
• Subjects: Ternary multiplexer -- Ternary half adder -- Ternary 3:1 mux -- Ternary logic -- Ternary decoder; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2019.05.007
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This work intends to prove that complex ternary combinational circuits can be custom designed using the conventional CMOS technology. This work focuses on implementing specific combinational circuits i.e. ternary 3 to 1 multiplexer circuit and Ternary Half Adder circuit in the conventional CMOS technology. In the binary digital system, it is known that any combinational logic can be implemented using multiplexer and basic logic gates. The same approach holds good in ternary logic as well. As almost any ternary combinational logic can be implemented using a ternary multiplexer, In this work it is proposed to design a fully customised ternary multiplexer. The proposed 3:1 ternary multiplexer will be used to design a ternary combinational circuit namely a Ternary Half Adder. As the aim of the work is to prove the feasibility of a ternary logic design on CMOS technology, the major attention is paid on realising the functionality of the ternary combinational circuits, rather than optimizing them for power. The circuits are designed and simulated in Cadence Virtuoso using 180 nm technology.