Impact of photovoltaic technology and feeder voltage level on the efficiency of façade building-integrated photovoltaic systems. (1st July 2020) - Ravyts, Simon; Moschner, Jens D.; Yordanov, Georgi H.; Van den Broeck, Giel; Dalla Vecchia, Mauricio; Manganiello, Patrizio; Meuris, Marc; Driesen, Johan
Highlights: Extensive modeling of all conversion steps from BIPV module to grid. The amount of derating is quantified and highly recommended for façade BIPV. Loss distribution is strongly impacted by the DC voltage level, efficiency not. A DC bus of 190 V is in overall most efficient for the examined cases. Lowering the DC bus voltage is advantageous for cost and efficiency. Abstract: Façade building-integrated photovoltaics is a technology that transforms a passive façade into a distributed, renewable electrical generator by the inclusion of solar cells in the building envelope. Partial shading due to nearby objects is a typical problem for façade building-integrated photovoltaics as it strongly reduces the output power of the installation. Distributed maximum power point tracking by means of embedded converters and a common direct current bus has been proposed to alleviate this issue. However, the bus voltage plays an important role in converter topology selection and overall efficiency, although this is not being covered in literature. Also the influence of the solar cell technology on the output voltage of the module is not studied before, although it strongly influences the converter topology selection and the losses. In this paper, a methodology is described to investigate the influence of the voltage level and solar cell technology by taking conversion losses in the converters and the cabling into account. The methodology is applied to two case study buildings for which four different cell technologies are considered. It is shown that overall high efficiencies are obtained, regardless of the voltage level. However, the loss distribution changes significantly with the voltage. This aspect can be used advantageously to reduce thermal stresses on the embedded converter. Furthermore, the overall system efficiency is typically higher when the voltage step-up is lower.